18:30 - 21:00 Registration
07:30 Registration & Breakfast
08:00 Opening Session
08:15 Session 1: Yield I
Chair: I. Koren - UMASS Amherst, U.S.A.
01.1 Manufacturability Analysis of Analog CMOS ICs Through Examination
of Multiple Layout Solutions
P. Khademsameni, M. Syrzycki
01.2 Effect of Static Power Dissipation in Burn-In Environment on Yield
and Reliability of VLSI
A. Vassighi, O. Semenov, M. Sachdev, A. Keshavarzi
01.3 Yield Estimates for the TESH Multicomputer Network
B. M. Maziarz, V. K. Jain
09:20 Session 2: Crosstalk Faults
Chair: R. Aitken - Agilent Technologies, U.S.A.
02.1 A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis
P. Civera, L. Macchiarulo, M. Violante
02.2 A Test-Vector Generation Methodology for Crosstalk Noise Faults
H. Hashempour, Y.-B. Kim, N. Park
10:05 Break
10:30 Session 3: Self-Checking and ABFT
Chair: F. M. Gonçalves - IST/INESC-ID, Portugal
03.1 A Parity Code Based Fault Detection for an Implementation of the
Advanced Encryption Standard
G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, V. Piuri
03.2 Designing Self-Checking FPGAs Through Error Detection Codes
C. Bolchini, F. Salice, D. Sciuto
03.3 Self-Checking Checker for 1-out-of-n Code Based on Current-Mode CMOS Logic
J. Mathew, E. Dubrova
03.4 Partially Duplicated Code-Disjoint Carry-Skip Adder
D. Marienfeld, V. Ocheretnij, M. Goessel, E. S. Sogomonyan
03.5 Input Ordering in Concurrent Checkers to Reduce Power Consumption
K. Mohanram, N. A. Touba
12:20 Lunch
13:50 Session 4: Fault Simulation and Injection I
Chair: Z. Koren - UMASS Amherst, U.S.A.
04.1 New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs
D. Alexandrescu, L. Anghel, M. Nicolaidis
(E. Dupont)
04.2 Injecting Bit Flips Faults by Means of a Purely Software Approach: A Case Studied
R. Velazco, A. Corominas, P. Ferreyra
04.3 Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm
H.-B. Wang, S.-Y. Huang, J.-R. Huang
14:55 Session 5: Scan Design
Chair: M. Rebaudengo - Politecnico di Torino, Italy
05.1 Scan Architecture Design for Shift and Capture Cycle Power
Reduction
P. M. Rosinger, B. M. Al-Hashimi, N. Nicolici
05.2 Inserting Test Points to Control Peak Power During Scan Testing
R. Sankaralingam, N. A. Touba
05.3 Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits
C.-H. Cheng
16:00 Break
16:25 Session 6: Test Application
Chair: M. Alderighi - CNR, Italy
06.1 Matrix-Based Test Vector Decompression Using an Embedded Processor
K. J. Balakrishnan, N. A. Touba
06.2 Data Compression for System-on-Chip Testing Using ATE
F. Karimi, W. Meleis, Z. Navabi, F. Lombardi
17:10 Session 7: Test Generation
Chair: X. Sun - University of Alberta, Canada
07.1 Fortuitous Detection and Its Impact on Test Set Sizes Using Stuck-At and Transition Faults
J. Dworak, J. Wingfield, B. Cobb, S. Lee, L.-C. Wang, M. R. Mercer
07.2 Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE
H. Hashempour, F. J. Meyer, F. Lombardi
07.3 Testing Digital Circuits with Constraints
A. A. Al-Yamani, S. Mitra, E. J. McCluskey
(N. A. Touba)
07:30 Registration & Breakfast
08:00 Session 8: Concurrent Error Detection
Chair: S. D'Angelo - CNR, Italy
08.1 On-Line Testing of Transient Faults Affecting Functional Blocks of
FCMOS, Domino and FPGA-Implemented Self-Checking Circuits
C. Metra, S. di Francescantonio, G. Marrale
08.2 Self-Checking and Fault Tolerance Quality Assessment Using Fault
Sampling
F. M. Gonçalves, M. B. Santos, I. C. Teixeira, J. P. Teixeira
08.3 A Memory Overhead Evaluation of the Interleaved Signature Instruction Stream
F. Rodríguez, J. C. Campelo, J. J. Serrano
08.4 Fault-Tolerant CAM Architectures: A Design Framework
F. Salice, M. G. Sami, R. Stefanelli
09:30 Session 9: Fault Simulation and Injection II
Chair: M. Margala - University of Rochester, U.S.A.
09.1 SEU-Like Injection Experiments Using Run-Time Reconfiguration
L. Antoni, R. Leveugle, B. Fehér
09.2 A Fault Hypothesis Study on the TTP/C Using VHDL-Based and
Pin-Level Fault Injection Techniques
S. Blanc, J. Gracia, P. J. Gil
09.3 Fault List Compaction Through Static Timing Analysis for Efficient
Fault Injection Experiments
M. Sonza Reorda, M. Violante
10:35 Break
11:05 Session 10: Interconnect
Chair: Y. Savaria, Ecole Polytechnique de Montréal, Canada
10.1 Performance of Deadlock-Free Adaptive Routing for Hierarchical
Interconnection Network TESH
S. Horiguchi, Y. Miura
10.2 Modeling of FPGA Local/Global Interconnect Resources and Derivation
of Minimal Test Configurations
X. Sun, A. Alimohammad, P. Trouborst
10.3 Testing Layered Interconnection Networks
F. Lombardi, N. Park
12:10 Lunch
13:40 Session 11: Yield II
Chair: W. Pleskacz - Warsaw University of Technology, Poland
11.1 Repair Yield Simulation with Critical Area Analysis for Each
Failure Type (CAA-EFT)
Y. Hamamura, K. Nemoto, T. Kumazawa, H. Iwata, K. Okuyama, S. Kamohara, A. Sugimoto
11.2 Yield Modeling of a WSI Telcom Router Architecture
B. Qiu, Y. Savaria, M. Lu, C. Wang, C. Thibeault
14:25 Session 12: System-on-Chip Test
Chair: T. M. Mak - Intel Corp., U.S.A.
12.1 Fast and Energy-Frugal Deterministic Test Through Test Vector
Correlation Exploitation
O. Sinanoglu, A. Orailoglu
12.2 Adaptive Test Scheduling in SoC's by Dynamic Partitioning
D. Zhao, S. Upadhyaya
15:10 Excursion to Capilano Suspension Bridge and Grouse Mountain
20:00 Banquet
08:00 Session 13: Feasibility of CED
Chair: C. Metra - University of Bologna, Italy
13.1 Duplication-Based Concurrent Error Detection in Asynchronous
Circuits: Shortcomings and Remedies
T. Verdel, Y. Makris
13.2 Feasibility Study of Designing TSC Sequential Circuits with 100%
Fault Coverage
S. J. Piestrak
08:50 Session 14: Test
Chair: M. Syrzycki - Simon Fraser University, Canada
14.1 Emulation-Based Design Errors Identification
A. Castelnuovo, A. Fin, F. Fummi, F. Sforza
14.2 A New Functional Fault Model for FPGA Application-Oriented Testing
M. Rebaudengo, M. Sonza Reorda, M. Violante
14.3 Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis
S. S. Sabade, D. M. H. Walker
14.4 CMOS Standard Cells Characterization for IDDQ Testing
W. A. Pleskacz, T. Borejko, W. Kuzmicz
14.5 On-Chip Jitter Measurement for Phase Locked Loops
T. Xia, J.-C. Lo
14.6 Neural Networks-Based Parametric Testing of Analog IC
V. Stopjaková, D. Micusik, L. Benusková, M. Margala
11:00 Break
11:25 Session 15: Reliable and Repairable Memories
Chair: R. Stefanelli - Politecnico di Milano, Italy
15.1 Balanced Redundancy Utilization for Dependable Embedded Memory
System Core
M. Choi, N. Park, F. Lombardi, Y.-B. Kim, V. Piuri
15.2 Repairability Evaluation of Embedded Multiple Subregion DRAMs
Y. Chang, M. Choi, N. Park, F. Lombardi
12:10 Closing Session
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